1. Field of the Invention
The present invention generates relates to a controllable delay logic circuit, and more particularly to an improvement in an arrangement of an emitter coupled logic circuit.
2. Description of the Related Art
There is known an emitter coupled logic circuit (hereinafter simply referred to as an ECL circuit) which is a high-speed digital logic circuit using a pair of transistors forming a current switch circuit. ECL circuits are widely used, as logic gates, in various large scale integrated circuits. An ECL circuit has an inherent propagation delay time. In some applications, the inherent propagation delay time of the ECL circuit is positively utilized. For example, a signal delay circuit is formed of the ECL circuit. A variable coaxial tube is known as an element capable of providing a precise signal propagation delay time.
Normally, the propagation delay time depends on various factors, such as the type of ECL circuit and device structure thereof, and are inherently determined at the time of completion of the production process. Thus, it is substantially impossible to adjust the propagation delay time after the production process. Nevertheless, there is a need to positively control the propagation delay time from the outside of the ECL circuit.
Referring to FIG. 1, there is illustrated a general ECL circuit. The ECL circuit in FIG. 1 has a pair of transistors T1 and T2 having emitters mutually connected. A constant-current source transistor T3 is connected between a power supply line coupled to a first low-potential side power source V.sub.EE1 and a node at which the emitters of the transistors T1 and T2 are mutually connected. Pull-up resistors R.sub.L are respectively connected between the collectors of the transistors T1 and T2 and a power supply line having a ground potential GND. A node at which the collector of the transistor T1 is connected to the pull-up resistor R.sub.L forms an output terminal x, which is connected to a base of an output transistor T4 which forms an output circuit of an emitter follower on the side of the transistor T1. Similarly, a node at which the collector of the transistor T2 is connected to the pull-up resistor R.sub.L forms an output terminal x, which is connected to a base of an output transistor T5 which forms an output circuit of an emitter follower on the side of the transistor T2.
An emitter follower circuit is composed of the transistors T4 and T5, resistors R.sub.T1 and R.sub.T2 respectively connected to the emitters of the transistors T4 and T5, and a second negative-side power source V.sub.EE2. It will be noted that the emitter follower circuit is not needed for the basic operation of the ECL circuit. However, the emitter follower circuit is usually provided in order to obtain a matching between the potential of an input signal and the potential of an output signal and increase load drivability of the ECL circuit. Due to the function of the emitter follower circuit, the voltages of the output terminals x and x are shifted, in parallel form, to signal output terminals X and X of the emitter follower circuit, respectively. The base of the constant-current source transistor T3 is supplied with a reference voltage V.sub.cs, which is a fixed potential. Signal input terminals IN, and IN are provided at the bases of the transistors T1 and T2, respectively.
When an input signal (H) having a potential higher than a potential of the signal input terminal IN is applied to the signal input terminal IN, the transistor T1 is turned ON. Thus, a constant current I.sub.cs passes through the transistor T3. The constant current I.sub.cs causes a voltage drop developed across the pull-up resistor R.sub.L. The voltage drop decreases the potential of a node (output terminal x) at which the collector of the transistor T1 and the pull-up resistor R.sub.L are connected to each other, so that the potential of the node becomes equal to a low (L) level. This low level is applied to the base of the output transistor T4. Thus, an inverted version of the input signal appears at the emitter of the output transistor T4, that is, the signal output terminal X of the emitter follower circuit. On the other hand, during the above-mentioned operation, the transistor T2 is turned OFF, and there is no voltage drop developed across the pull-up resistor R.sub.L connected to the collector of the transistor T2. Thus, the base potential of the transistor T5 is approximately equal to the ground potential GND. As a result, a signal (H) in phase with the input signal appears at the output terminal x and the emitter of the transistor T5, that is, the signal output terminal X. In the case where the potential of the input signal applied to the signal input terminal IN is lower than the potential of the input terminal IN, the circuit operates in a way opposite to the above-mentioned operation. Thus, a high-potential output signal is obtained at the signal output terminals x and X, and a low-potential output signal is obtained at the output terminals x and X.
A propagation delay time t.sub.pd of the ECL circuit shown in FIG. 1 is expressed as follows. EQU t.sub.pd =A.multidot.rb.multidot.C.sub.cb +B.multidot.rb.multidot.C.sub.be +C.multidot.C.sub.bc .multidot.(R.sub.L +re)+D.multidot.C.sub.be re+E.multidot.C.sub.sub .multidot.(R.sub.L +re)+F.multidot.C.sub.L .multidot.(R.sub.L +re)+t.sub.pd EF (1)
where A through E are proportion coefficients, and t.sub.pd EF is a propagation delay time provided by the emitter follower circuit. Further, the following symbols denotes parameters of the transistors T1 and T2:
C.sub.cb : base-collector junction capacitance PA1 C.sub.be : base-emitter junction capacitance PA1 C.sub.sub : collector-substrate junction capacitance PA1 C.sub.L : parasitic capacitance between pull-up resistor R.sub.L and wiring lines PA1 rb: base resistance PA1 re: sum of an emitter resistance and differentiating resistance of the base-emitter forward characteristic.
That is, the propagation delay time t.sub.pd of the ECL is as follows ##EQU1## The term t.sub.pd is not related to the present invention, an is thus handled so that it is zero. The formula (2) means that the propagation delay time t.sub.pd corresponds to the sum of the products of the resistances and the corresponding capacitances, and is thus based on the time constant defined by a formula, .tau.=R.multidot.C.
FIG. 2 is a waveform diagram illustrating how the propagation delay time t.sub.pd of the ECL circuit shown in FIG. 1 is generated. In FIG. 2, V.sub.IN denotes an input voltage applied to the signal input terminal IN shown in FIG. 1, and V.sub.IN denotes an input voltage applied to the input terminal IN shown in FIG. 1. Further, V.sub.X denotes an output voltage obtained at the signal output terminal X, and V.sub.X denotes an output voltage obtained at the signal output terminal X. The propagation delay time t.sub.pd corresponds to a period between a time when the input voltage difference between V.sub.IN and V.sub.IN corresponds to 50% (that is, 0 volt) of the maximum difference and a time when the output voltages V.sub.X and V.sub.X correspond to 50% of the maximum amplitudes. As shown in FIG. 2, the rise and fall of the output voltages V.sub.X and V.sub.X lag behind those of the input voltages V.sub.IN and V.sub.IN by the propagation delay time t.sub.pd. The slope of the rise (or fall) of the output voltage obtained at each of the signal output terminals X and X is based on the time constant of the pull-up resistor R.sub.L and the parasitic capacitance C.sub.L as well as the constant current I.sub.cs.
In order to adjust the propagation delay time t.sub.pd from the outside of the ECL circuit, one may try to change a reference voltage V.sub.cs applied to the base of the constant-current transistor T3 so that the constant current I.sub.cs is changed and thus the amplitude of the output voltage is changed.
However, the above consideration is not effective to control the propagation delay time t.sub.pd from the outside of the ECL circuit for the following reasons. First, the aforementioned formula (1) does include the term of the constant current I.sub.cs. That is, the constant current I.sub.cs does not contribute to changing the propagation delay time t.sub.pd. Although the amplitude of the output voltage V.sub.X (V.sub.X) is changed by changing the constant current I.sub.cs, the rising slope and falling slope of the output voltage are also changed. As a result, there is less change in the propagation delay time t.sub.pd, and the circuit operation is instable. More specifically, when the reference voltage V.sub.cs is controlled so that the current passing through the transistor T3 increases, an increased voltage drop developed across the pull-up resistor R.sub.L is obtained and thus an increased amplitude of the output signal is obtained. However, an increase in the current increases the load drivability, which accelerates the circuit operation. Thus, it is possible to control the propagation delay time within only a narrow range.